For applications like ultra low power radio receivers, analog-to-digital converters (ADC) with a low resolution (4 or 5 bits) and high speed of operation (at least 500 MS/s) are required. Especially, the power efficiency of the ADC is important, since the overall radio's power consumption should be minimized. Current low resolution ADCs are typically not power efficient, unless a substantial amount of calibration is used. For high-speed (>100 MS/s), low-resolution (4 to 6 bits) ADCs typically flash or folding topologies are used. However, these architectures are not the most power efficient ones.
An important aspect for an ADC's power consumption is the number of comparisons required for each conversion. Table 1 shows an overview of the amount of comparisons per conversion for various ADC architectures, assuming an N-bit resolution.
TABLE 1Comparisons perArchitectureconversionFlash2NFolding2N−MPipelineN . . . 2NSAR, binary-searchNSlope/ramp1
For high-speed (>100 MS/s), low-resolution (4-6 bit) ND converters, typically flash or folding topologies are used. However, based on Table 1, it can be expected that these architectures are not the most power-efficient ones. Current state-of-the-art converters can achieve power efficiencies in the order of 40-200 fJ per conversion step. However, this is only achievable when using substantial calibration techniques to correct for the comparator offsets. In reality, this calibration can be cumbersome and strongly dependent on environmental conditions (temperature, supply voltage). Without calibration, the power efficiency would be significantly degraded.
Document EP 0564143 A2 relates to a multi-mode successive approximation analog-to-digital converter that converts an analog input signal into a digital value according to a linear or companding transfer function. The converter comprises a comparator, a successive approximation register and a charge redistribution device. A plurality of capacitors of different size is used whereby the capacitor terminals on one side are selectively connected to a different reference voltage in a successive approximation approach.
U.S. Pat. No. 4,985,702 discloses an ND converter with second error correction that provides a more accurate digital output code for a HF input analog signal. A slope (i.e. slew rate) of the input signal is determined from the digital output code of a quantizer and the slope is used to provide a correction value that is a function of the slope.
In U.S. Pat. No. 5,933,039 a digital signal delay line is presented with electrically programmable and trimmable delay times, including electrically erasable and reprogrammable delay times.